We’re Hiring Physical Design Engineer – Advanced Node (3nm / 3D IC)

Physical Design Engineer Advanced Node (3nm / 3D IC) 2. Location, Work Mode, Experience Range

• Location: Bangalore, India
• Work Mode: Onsite
• Experience Range: 5+ Years

3. Role Overview

• Responsible for end-to-end physical design implementation for advanced node (3nm) semiconductor chips.
• Focus on chip top-level integration and exposure to 3D IC and chiplet-based architectures.
• Work across the full RTL-to-GDSII flow, collaborating with cross-functional teams.
• Contribute to achieving power, performance, and area (PPA) targets for complex SoCs.

4. Key Responsibilities

• Execute block-level and top-level physical design implementation for advanced node ASICs.
• Drive full chip RTL-to-GDSII flow including floorplanning, placement, CTS, routing, and signoff.
• Perform timing closure across multiple corners and modes using STA methodologies.
• Conduct physical verification including DRC, LVS, and ERC checks.
• Perform parasitic extraction and timing/power analysis.
• Optimize designs for power, performance, and area (PPA).
• Work on chip top integration, hierarchical design, and large SoC assembly.
• Contribute to 3D IC design including chiplet integration and die-to-die interfaces.
• Debug design, convergence, and flow issues across implementation stages.
• Collaborate with front-end, packaging, and foundry teams for tape-out readiness.
• Support tape-out activities and post-layout validation.
• Develop and maintain automation scripts for design and flow efficiency.

5. Required Qualifications

• Bachelor’s degree in Electronics / Electrical Engineering; Master’s preferred (VLSI / Microelectronics).
• 5+ years of experience in physical design for ASIC/SoC development.
• Hands-on experience with advanced nodes (5nm / 3nm preferred).
• Proven experience in full chip or block-level tape-outs.

6. Technical Skills (Grouped & Structured)Physical Design & Implementation

• RTL to GDSII flow
• Floorplanning, Placement, CTS, Routing
• Chip top integration, hierarchical design

Timing & Signoff

• Static Timing Analysis (STA)
• Timing closure (multi-mode, multi-corner)
• Signal integrity and noise analysis

Verification & Analysis

• DRC, LVS, ERC
• Parasitic extraction (PEX)
• Power analysis and IR drop

EDA Tools

• Cadence Innovus (preferred)
• Synopsys ICC2 / Fusion Compiler
• Mentor Graphics (Calibre)

Advanced Technologies

• 3nm / 5nm process nodes
• 3D IC, chiplet architecture
• Die-to-die interfaces, advanced packaging

Scripting & Automation

• Tcl, Perl, Python

Fundamentals

• CMOS technology
• Semiconductor device physics
• Digital circuit design

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